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1/28 l6611 april 2002 n ov/uv detection for 3.3v, +5v, 12v rails and 5v (or 3.3v) aux. voltage n ac mains uv (brownout) detection with hysteresis n on-line digital trimming for 5v/12v, 3.3v, 5v (or 3.3v) aux. feedback references and ac mains uv. n digitally selectable options n error amplifiers for 5v/12v rails (main supply), 3v3 post-regulator (mag_amp or linear) and auxiliary supply. n main supply on/off control and power good signal n 50ma crowbar drive for auxiliary output ovp. n open ground protection n 8ms digital soft start n 64 ms uv/oc blanking at start-up applications n switching power supplies for desktop pc's, servers and web servers n supervisor for distributed power dip20 so20 ordering numbers: l6611n l6611d L6611DTR(t & reel) digitally programmable secondary housekeeping controller typical application circuit +5vaux wide range mains +5v com +3.3v +12v - + main control auxiliary control vdd 12v cout gnd mfault aout 5v 3v3 l6611 -12v -12v dmon bout bcd technology
l6611 2/28 block diagram +3v3 +12v vdd ov logic and programmable trimming prog cinv cout dmon vdd 2.50v(b) uv ov ocp bounce l vdd v u f reset 1.25v (a) 2.50v( a) v r e 2.50v( b) debounce 75ms 2.50v( c) 10ma gnd bout aout binv ainv soft start 2.50v(a) +5v +12v 1.25v (b) ov disable uv ov uv uv ov ov uv 2.50v(b) dfault ps -on / clock vreg pw -ok / data mfault acsns -12v +12v +5v +5v +3v3 50ua ov vdd programming input +/-12v uv 3v3 +5v uv uv vdd + _ 2.50v(b) 2.50v( c) 1.25v( a) 1.25v(b) v - - - + _
3/28 l6611 description the l6611 is a control and housekeeping ic developed in bcd technology; it is intended for acting at the sec- ondary side of desktop pc's or server's switching power supplies, in presence of standard voltage rails (+3.3v, +5v, 12v) generated by a main converter and of a supply line generated by an auxiliary converter. the typical application circuit is showed on the front page. the housekeeping's main function is to control and monitor the voltages generated by both the main and the auxiliary converter: it senses those voltages, sends feedback signals to the primary controllers for regulation and, upon detection of an undervoltage (uv), or overvoltage (ov) condition, reports such fault and takes proper action to protect the system. however, the peculiar feature of this ic is its digital programming capability that enables an accurate trimming of the output voltage rails during production test via software, without any use of external discrete trimming com- ponents or need for manual intervention on the psu. it is also possible to program some of the monitoring func- tions and select how uv and oc conditions are handled in the main converter: whether latched-mode (the information is latched and released only by forcing the restart of the ic) or bouncing-mode (an attempt is made to automatically restart the converter after 1 second wait). a key feature of this ic is its contribution to a very low external component count. besides the extensive use of onboard programmable switches, which prevents the need for external trimming components, the ic embeds reference voltages, error amplifiers and most of the housekeeping circuitry normally required. pin connection (top view) pin description pin # name description 1 mfault main converter on/off control. this pin is a 10ma current sink used for driving an opto-isolator. it is normally low when ps-on (#13) is pulled low. if a fault is detected or ps-on goes high, this pin goes high too. to allow power up, the functions are digitally blanked out for a period (uvb function) and mfault (#1) stays low. there is no delay for the ov protection function. 2 binv inverting input to the error amplifier for the 3v3 post-regulator (either mag-amp or linear). the non-inverting input is connected to an internal 1.25v reference that can be digitally trimmed. 3 bout output of the 3v3 error amplifier. it typically drives either a pnp transistor that sets the mag-amp core or the pass element of a linear regulator. also node for error amplifier compensation. the maximum positive level of this output is clamped at about 3.5v to improve response time. large signal slew rate is limited to reduce noise sensitivity. mfault binv bout 12v 5v 3v3 -12v vref ps-on pw -ok acsns vdd dfault dmon cout aout ainv prog cinv gnd - - mfault binv bout 12v 5v 3v3 -12v vref ps-on pw -ok acsns vdd dfault dmon cout aout ainv prog cinv gnd - -
l6611 4/28 4 aout output of the error amplifier for the main converter. this pin typically drives an optocoupler and is also used for compensation along with ainv (pin #5). 5 ainv main loop error amplifier inverting input. the non-inverting input is connected to an internal 2.5v reference that can be digitally trimmed. a high impedance internal divider from +12v and +5v uv/ov sense pins (#19, #20) eliminates the need for external divider in most applications. the pin is used for error amplifier compensation. 6 cout auxiliary loop optocoupler drive. also node for error amp compensation. large signal slew rate is limited to reduce sensitivity to switching noise. 7 cinv inverting input for auxiliary error amplifier. the non-inverting input is connected to an internal 1.25v reference that can be digitally trimmed. 8 dmon dual or auxiliary uv/ov monitor, dmon is programmable to monitor 3v3 or 5v. to allow a correct power up, the uv function on this pin is blanked out during initial start-up. there is no delay for the ov function. 9 dfault dual or auxiliary fault protection. when dmon (#8) recognizes an over voltage, dfault and mfault (#1) go high. dfault is capable of sourcing up to 50ma. possible applications are a crowbar across the auxiliary output or an opto-coupled fault signal to the primary side. 10 vdd positive input supply voltage. vdd is normally supplied from the auxiliary power supply output voltage. if vdd-uvl detects a sustained under voltage, pw-ok (#12) will be pulled low and sending mfault (#1) high will disable the main converter. 11 acsns analo g of bulk volta g e for ac fail warnin g . the usual source of this analo g pin is one of the secondar y windin g s of the main transformer. h y steresis is provided throu g h a trimmable 50 m a current sink on this pin that is activated as the volta g e at the pin falls below the internal reference (2.5v). 12 pw-ok /data power good signal for the main converter. when asserted high, this pin indicates that the voltages monitored are above their uv limits. there will be typically 250ms delay from the main outputs becoming good and pw-ok being asserted. this is nominally an open drain signal. to improve robustness, this output has a limited current sink capability. in programming mode, this pin is used for data input; then the absolute maximum rating will be vdd+0.5v. 13 ps-on / clock control pin to enable the main converter. this pin has debouncing logic. a recognized high value on this pin will cause pw-ok (#12) to go immediately low and, after a delay of 2.5ms, to shut down the main pwm by allowing mfault (#1) to go high. during normal operation (or if not used) this pin has to be connected to a voltage lower than 0.8v. in programming mode, this pin will be used to clock serial data into the chip. 14 vref 2.5v reference for external applications. this is a buffered pin. shorting this pin to ground or to vdd (#10) will not affect integrity of control or monitor references. an external capacitor (max. 100nf) is required whenever the pin is loaded (up to 5 ma), otherwise it can be left floating. 15 -12v -12v uv/ov monitor. if connected to a voltage greater than 1.5v (e.g. vref, #14), the function will be disabled. 16 gnd ground pin. the connection integrity of this pin is constantly monitored and in case of either a bond wire or a pcb trace going open, mfault (#1) and dfault (#9) will be forced high switching off the supply. 17 prog the chip has 2 operating modes, depending on prog input pin biasing: C normal mod e: prog should be floating or shorted to ground; C programming mod e: forcing prog high (+5v), the chip enters programming mode. pw_ok (#12) and ps_on (#13) pins are disconnected from their normal functionality and they become inputs for data and clock allowing the chip to be programmed. the programming mode al- lows selecting some options and adjusting some setpoints; pin description (continued) pin # name description
5/28 l6611 18 3v3 3v3 uv/ov monitor. it uses a separate reference to the feedback reference. 19 5v input pin for 5v feedback, 5v current sense and 5v uv/ov monitor. 5v uv/ov uses a reference separate from that used for feedback. this pin connects the 5v part of the main error amplifier feedback divider. 20 12v input pin for 12v feedback, 12v current sense and 12v uv/ov monitor.12v uv/ov uses a reference separate from that used for feedback. this pin connects the 12v part of the main error amplifier feedback divider. function description name description ovp whenever one of the main output voltages is detected going above its own ovp threshold, this function set mfault (#1) high latching the outputs off. the latch is released after cycling ps-on (#13) switch or by reducing vdd (#10) below the uv threshold. uvp whenever one of the main output voltages is detected going under its own uvp threshold, this function sets mfault (#1) high; if latch mode has been selected, this function will be latched. otherwise an attempt will be made to restart the device after 1 second delay. if acsns (#11) is low due to a brownout condition, uvp is disabled. uvb undervoltage blanking. when either converter is enabled, the relevant uv/oc monitoring circuits must not intervene to allow all outputs to come within tolerance. 64 ms timing is provided; for the auxiliary converter the timing starts as the ic has a valid supply, for the main converter it starts as the acsns pin detects a valid input voltage for the converter. pw-ok delay pw-ok delay. after power-up, when the all of the monitored voltages are above their own uv threshold the pw-ok pin (#12) will be kept low for additional 250ms (typ.) to make sure all the outputs are settled. off delay power-off delay. as soon as ps-on (#13) pin is recognized high, indicating an imminent turn-off condition, pw-ok (#12) pin will go low immediately . the converter will be turned off after a delay of 2.5ms. debounce the ps-on signal input has debounce logic to prevent improper activation. all of the monitored inputs have digital filtering/debounce logic on board for high noise immunity. ac-hysteresis ac sense hysteresis. programmable hysteresis is provided on the acsns input (#11) to avoid undesired shutdown caused by noise as the voltage at the pin is near the threshold or by the voltage ripple across the bulk capacitor. vdd-ovp vdd is monitored for overvoltage. if an overvoltage is detected, mfault (#1) and dfault (#9) are latched high. vdd-uvl to prevent false signals of any of ics output pins, an under voltage lock-out circuit monitors vdd and keeps all ics output at their default off level until vdd reaches a sufficient minimum voltage for ensuring integrity. when vdd goes below the uv threshold, all latches are reset and volatile programming memory cleared. dual-ovp dmon (#8) is monitored to detect an overvoltage condition; in this case mfault (#1) and dfault (#9) are latched high. dual-uvp dmon (#8) is monitored to detect an undervoltage condition; in this case mfault (#1) is latched high and cout (#6) is pulled low. pin description (continued) pin # name description
l6611 6/28 absolute maximum ratings thermal data (*) mounted on board soft-start the ic provides an on-board 8ms soft-start, a quasi-monotonic ramp from 0v to 2.5v for the a error amplifier reference voltage, in order to avoid high current peaks in the primary circuit and output voltage overshoots at start-up. in fact, if this reference gets the nominal value as soon as the power-up occurs, the a e/a will go out of regulation and tend to sink much more current, thus forcing pwm to work with the maximum duty-cycle. bounce or latch-mode this option allows setting either latched-mode or auto restart after 1 second delay in case of undervoltage faults. symbol parameter value unit vdd supply voltage -0.5 to +7 v voltage on prog, ps-on/clock, dfault, vref, and error amplifier pins -0.5 to vdd+0.5 v voltage on mfault, pw-ok, dmon and positive uv, ov, oc, ac sense pins. -0.5 to +16 v voltage on and -12v uv/ov sense pin -16 to +5 v maximum current in esd clamp diodes 10 ma t j operating junction temperature -25 to 150 c t sto storage temperature -50 to 150 c t l lead temperature (soldering, 10 seconds) 300 c symbol parameter dip20 so20 unit r th j-amb max. thermal resistance junction-to-ambient (*) 70 120 c/w function description (continued) name description
7/28 l6611 electrical characteristcs (unless otherwise specified: t j = 0 to 105c; v dd = 5v, v 3v3 = 3.3v, v 5v = 5v, v -12v = -12v, , v dmon = v dd , ps-on = low) symbol parameter test condition min. typ. max. unit supply section v dd(on) start-up threshold 4.2 4.3 4.6 v v dd(off) minimum operating voltage after turn-on 3.7 3.8 4.1 v v dd(h) hysteresis 0.25 0.5 0.75 v v ddov vdd overvoltage 6.1 6.3 6.8 v i dd-on operating supply current no fault 5 7 ma fault thresholds vout = 3.3v uv 3v3 undervoltage 2.80 2.90 3.00 v ov 3v3 overvoltage 4.00 4.15 4.30 v 3v3 bias current 50 65 m a vout = 12v uv 12v undervoltage 10.60 10.80 11.00 v ov 12v overvoltage 13.50 14.00 14.50 v 12v bias current 100 130 m a vout = -12v uv -12v undervoltage -9.00 -9.50 -10.0 v ov -12v overvoltage -14.4 -15.0 -15.6 v v d -12v disable voltage voltage to disable comparator 1.3 1.5 1.7 v -12v bias current -65 -50 m a vout = 3.3v aux/dual (dmon option) uv 3v3 undervoltage 2.80 2.90 3.00 v ov 3v3 overvoltage 4.00 4.15 4.30 v vout = 5v aux/dual (dmon option) uv 5v undervoltage 4.25 4.40 4.55 v ov 5v overvoltage 6.00 6.25 6.50 v bias current 50 65 m a acsense / hysteresis bias current v acsns = 2.7v 5 10 m a
l6611 8/28 uv ac undervoltage 2.375 2.50 2.625 v trim range -5 +5 % trim resolution 0.64 % i ach hysteresis current 20 50 80 m a hysteresis trim range -20 +20 % h s hysteresis adjust step 5 % fault outputs v pokh pw-ok high state no faults 3 v v pokl pw-ok low state i sink = 15ma 0.4 v i l mfault high state leakage ps-on = high 1 m a mf isnk mfault sink current ps-on = low, v mfault = 4v 6 10 15 ma mfault ov debounce minimum ov pulse before mfault is latched. 468 m s mfault debounce 12v uv minimum uv pulse before mfault is latched. 468 m s mfault debounce +5v, 3v3, uv minimum uv pulse before mfault is latched. 250 450 650 m s df ioh dfault output high source current overvoltage condition v dfault = 1.5v -25 -50 -95 ma d fvoh dfault output high voltage i dfault = 0ma, t amb = 25 o c, overvoltage condition 2.1 2.4 2.7 v v out dfault output low voltage i dfault = 1ma, no faults 0.3 0.5 0.7 v dfault ov debounce minimum ov pulse before dfault is latched. 468 m s dfault uv debounce minimum uv pulse before dfault is latched. 250 450 650 m s start-up / shutdown functions t5 dfault uv blanking delay delay from v dd (on) to dfault uv active. 44 64 84 ms t1 mfault uv blanking delay delay from ac sns high to main uv active 44 64 84 ms t2 pw-ok blanking delay mains uv good to pw-ok high 175 250 325 ms t4 (t delay ) ps-on delay time delay from ps-on input to mfault 1.75 2.5 3.25 ms electrical characteristcs (continued) (unless otherwise specified: t j = 0 to 105c; v dd = 5v, v 3v3 = 3.3v, v 5v = 5v, v -12v = -12v, , v dmon = v dd , ps-on = low) symbol parameter test condition min. typ. max. unit
9/28 l6611 v ih ps-on input high voltage i in = -200 m a 2.0 v v il ps-on input low voltage 0.8 v ps-on input high clamp i ps-on = 100 a vdd +0.7 v r ps-on ps-on pull-up to v dd v ps-on = 0v 25 50 100 k w t3 ps-on debounce ps-on input minimum pulse width for a valid logic change. 50 75 100 ms t ss error amp. a soft-start period vfb quasi-monothonic ramp from 0 to 2.5v 8ms v step soft start step ramp 0v to 2.5v 39 mv voltage reference (buffered external pin) v ref output voltage i ref = 1 - 5 ma; c ref = 47nf 2.375 2.50 2.625 v i sc short circuit current v ref = 0 10 20 ma main converter feedback (error amplifier a) v fb input voltage t j = 25 c 2.375 2.50 2.625 v trim range about nominal -5 +5 % trim resolution 0.64 % z fb divider impedance from ainv to gnd. 5v and 12v connected to gnd. 35 50 65 k w temperature coefficient 26 w / c w 5 divider 5/12 weighting 5v contribution to 5/12 feedback 47 50 53 % a vol voltage gain 2v l6611 10/28 trim resolution 0.64 % i bias input bias current -0.1 -1 m a a vol voltage gain 2v 11/28 l6611 f clock clock frequency 0.8 mhz v datalo data input low 1.5 v v datahi data input high 2 v i fuse prom fuse current 400 ma t fuse prom fusing time 3 ms electrical characteristcs (continued) (unless otherwise specified: t j = 0 to 105c; v dd = 5v, v 3v3 = 3.3v, v 5v = 5v, v -12v = -12v, , v dmon = v dd , ps-on = low) symbol parameter test condition min. typ. max. unit
l6611 12/28 figure 1. supply start-up, uv and ov figure 2. ic supply current vs. supply voltage figure 3. ic supply current figure 4. monitored inputs bias current figure 5. 3.3v fault thresholds figure 6. 5v fault thresholds 3.5 4.5 5.5 6.5 -50 -25 0 25 50 75 100 125 150 uv start-up over voltage v dd [v] t [ o c] v dd [v] 0246810 0 2 4 6 8 10 i dd [ma] dmon = v dd t j = 25 c 3 4 5 6 7 -50 -25 0 25 50 75 100 125 150 i dd [ma] t [ o c] 30 40 50 60 70 80 -50-250 255075100125150 3.3voutput 5voutput 12voutput t [ o c] i b [ m a] 2 3 4 5 -50 -25 0 25 50 75 100 125 150 t [ o c] undervoltage overvoltage v 3.3v [v] 3 4 5 6 7 -50 -25 0 25 50 75 100 125 150 t [ o c] overvoltage undervoltage v 5v [v] typical electrical characteristics
13/28 l6611 figure 7. 12v fault thresholds figure 8. 3.3v/5v dmon fault thresholds figure 9. -12v bias current figure 10. -12v fault thresholds figure 11. acsense and external voltage references figure 12. error amplifier a, b and c reference voltage 10 11 12 13 14 15 -50 -25 0 25 50 75 100 125 150 t [ o c] overvoltage undervoltage v +12v [v] -18 -15 -12 -9 -6 -3 0 -50 -25 0 25 50 75 100 125 150 +3.3v undervoltage +5v undervoltage +5v overvoltage +3.3v overvoltage t [ o c] v dmon [v] -50 -40 -30 -20 -50-25 0 255075100125150 -18 -15 -12 -9 -6 -50 -25 0 25 50 75 100 125 150 overvoltage undervoltage 2.3 2.4 2.5 2.6 2.7 -50 -25 0 25 50 75 100 125 150 t [ o c] [v] 0.5 1 1.5 2 2.5 3 -50 -25 0 25 50 75 100 125 150 t [ o c] [v] a b - c typical electrical characteristics (continued)
l6611 14/28 figure 13. error amplifiers (a, b, c) gain and phase 200 150 100 50 0 -50 -100 -150 -200 1e+00 1e+01 1e+02 1e+03 1e+04 1e+05 1e+06 1e+07 7e+07 90 o 0 o m f gain phase 200 150 100 50 0 -50 -100 -150 -200 1e+00 1e+01 1e+02 1e+03 1e+04 1e+05 1e+06 1e+07 7e+07 90 o 0 o m f gain phase 180 o typical electrical characteristics (continued)
15/28 l6611 application information index 1 on board digital trimming and mode selection..................................................................................p age 16 2 error amplifiers and reference voltages ........................................................................................ ............. 18 main section: error amplifier a and soft -start e/a and reference voltage 3.3v section: error amplifier b auxiliary section: error amplifier c 3 normal operation timing diagram ................................................................................................ ............... 20 4 undervoltage, overvoltage and relevant timings ................................................................................. ....... 21 5 ac sense (mains undervoltage warning) .......................................................................................... ......... 22 6 application example ............................................................................................................ ....................... 23 7 application ideas .............................................................................................................. .......................... 25
l6611 16/28 application information 1 onboard digital trimming and mode selection by forcing the prog input pin high, the chip enters programming mode: the multifunction pins pw_ok and ps_on are then disconnected from their normal functions (output pins) and are connected to internal logic as data and clock inputs respectively, allowing chip programming even when the device is assembled on the application board. onboard chip programming allows: C selecting some working options; C reference voltage setpoints adjusting. it is also possible to verify the expected results before programming the chip definitively, in first instance, data can be loaded into a re-writeble volatile memory (a flip-flop array) where they are kept as long as the chip is supplied and can be changed as many times as one desires. a further operation is necessary to confirm the loaded data and permanently store them into a prom (a poly-fuse array) inside the ic. several steps compose the trimming/programming process: 1. prog pin is forced high; 2. a clock signal is sent to the ps-on/clock pin; 3. a byte with the following structure: is serially sent to the pw-ok/data pin and loaded into the ic's volatile memory bit by bit on the falling edges of the clock signal (see fig. 14); "address" is the identification code of the parameter that has to be trimmed and "data" contains the tuning bits; 4. prog pin is forced low (warning: vdd must never fall below v dduvl0 during this process otherwise the con- tents of the volatile memory will be lost) and the result of the previous step is checked; 5. after any iterations of the steps 1-4 that might be necessary to achieve the desired value, force prog pin high and send the following burn code to permanently store the data in the prom memory. table 1 shows the list of the 6 programmable classes of functions, each one identified by a different code a0..a3, and the corresponding trimmable parameter(s); in table 2 it is possible to find the trim coding for the e/ a reference setpoints and in table 3 all the selections mode option coding are showed. the timing diagram of fig. 14 shows the details of data acquisition. table 1. programmable functions msb lsb d3 d2 d1 d0 a3 a2 a1 a0 data address msb lsb 00001111 address parameter(s) default value tuning bits 0001 error amplifier a threshold 2.50v d 3 d 2 d 1 d o 0010 error amplifier b threshold 1.25v d 3 d 2 d 1 d o 0011 error amplifier c threshold 1.25v d 3 d 2 d 1 d o 0100 ac sense threshold 2.50v d 3 d 2 d 1 d o 0101 ac sense hysteresis 50 m a d 2 d 1 d o latch/bounce mode selection latch mode d 3 0110 enable/disable 12v uv/ov function enabled d 3 enable/disable 5v uv/ov function enabled d 2 5v/3v3 dmon selection 5v selection d 1 dont care
17/28 l6611 table 2. trim coding table 3. mode coding figure 14. trimming/programming procedure: timing diagram parameter e/a a threshold 2.5v typ. e/a b threshold 1.25v typ. e/a c threshold 1.25v typ. acsns threshold 2.5v typ. acsns hysteresys 50 m a typ. address 0001 0010 0011 0010 0101 tuning bits d 3 d 2 d 1 d 0 d3 d2 d1 d0 d v [mv] d3 d2 d1 d0 d v [mv] d3 d2 d1 d0 d v [mv] d3 d2 d1 d0 d v [mv] d2 d1 d0 d i [ m a] 0 1 1 1 +112 +56 +56 +112 0 1 1 0 +96 +48 +48 +96 0 1 0 1 +80 +40 +40 +80 0 1 0 0 +64 +32 +32 +64 0 0 1 1 +48 +24 +24 +48 +7.5 0 0 1 0 +32 +16 +16 +32 +5.0 0 0 0 1 +16 +8 +8 +16 +2.5 0 0 0 0 00000 1 1 1 1 -16 -8 -8 -16 -2.5 1 1 1 0 -32 -16 -16 -32 -5.0 1 1 0 1 -48 -24 -24 -48 -7.5 1 1 0 0 -64 -32 -32 -64 -10 1 0 1 1 -80 -40 -40 -80 1 0 1 0 -96 -48 -48 -96 1 0 0 1 -112 -56 -56 -112 1 0 0 0 -128 -64 -64 -128 parameter bounce or latch mode enable/disable 12v uv/ov enable/disable 5v uv/ov 5v/ 3.3v dmon selection address a3 a2 a1 a0 0101 a3 a2 a1 a0 0110 bit value tuning bit d3 d3 d2 d1 0 latch enabled enabled 5v 1 bounce disabled disabled 3.3v 1 0 0 0 0 0 1 1 msb lsb prog ps_on/clock pw_ok/data
l6611 18/28 2 error amplifiers and reference voltages three error amplifiers are implemented on the ic to achieve regulation of the output voltages: a brief description follows for each section. C main section: error amplifier a and soft-start. the circuit is designed to directly control the main primary pwm through an optocoupler, providing very good regulation and galvanic isolation from the primary side. typical solutions require a shunt regulator, like the tl431, as a reference and feedback amplifier to sense the output voltage and gen- erate a corresponding error voltage; this voltage is then converted in a current transferred to the pri- mary side through the optocoupler. the feedback e/a amplifier is integrated in the ic: its non-inverting input is connected to an internally gen- erated voltage reference, whose default value is typically 2.5v. it can however be trimmed to obtain a better precision (see "on board trimming and mode operating" section). then, no tl431 is needed. the e/a inverting input (ainv, pin#5) and the e/a output (aout, pin#4) are externally available and the frequency compensation network (zc) will be connected between them (see fig. 15). the high impedance (in the hundred k w ) internal divider from 12v and 5v uv/ov sense pins elimi- nates the need for an external one in most applications, allowing a further reduction in the number of external component. under closed loop condition, the two upper branches, connected to 12v and 5v pins, supply equally the current flowing through r3= 80.6k (equal to 2.5v/r3). in order to avoid high current peaks in the primary circuit and output voltage overshoots at start-up, the ic provides an on-board 8ms soft-start, a quasi-monotonic ramp from 0v to 2.5v for the a error amplifier reference voltage,. in fact, if this reference gets the nominal value as soon as the power-up occurs, the a e/a will go out of regulation and tend to sink much more current, thus forcing pwm to work with the maximum duty-cycle. C e/a and references voltage being the inverting input of e/a externally available, it is possible to change the "weight" of the two contributions or even eliminate one of them by connecting external resistors of much lower value (r l , r h1 and/or r h2 in fig. 15) that bypass the internal ones appropriately. for example using r l =2.4k, r h1 =3.9k and r h2 =24k, then the ratio between +5v and +12v output weight will be equal to 6:4. by simply making r h1 = r l (for example 2.4k) with no r h2 , only the +5v output is kept under feed- back because the contribution of +12v branch (through the internal 600k resistor) will be negligible. the pin #24 (12v) has to be connected to +12v output to guarantee the ov/uv monitoring. figure 15. main feedback section C 3.3v section, error amplifier b. it is the error amplifier used to set the magamp core through an external circuitry (see a typical sche- matic in figure 16). the non-inverting input of the error amplifier is connected to a trimmable 1.25v internal voltage ref- erence (see "on board trimming and mode operating" paragraph). the e/a inverting input is exter- nally available (binv, pin#2) and is connected to the output divider (r h and r l ); the output pin (bout, v dd to main control zc aout r b 12v 5v +2.5v 600k 168k 80.6k 8ms ss l6611 gnd _ + +12v output +5v output ainv r l r h1 r h2 optional, to change feedback weight v dd to main control zc aout r b 12v 5v +2.5v 600k 168k 80.6k 8ms ss l6611 gnd _ + +12v output +5v output ainv r l r h1 r h2 optional, to change feedback weight
19/28 l6611 pin#3) drives the external circuitry that biases the magamp core. between these pins it is connected the compensation network (z c ). the maximum positive output voltage is clamped at about 3.5v to improve response time. the feedback control circuit determines the magamp "off" time, converting the voltage at the output of error amplifier into a current i r , which resets the magamp. if the output voltage exceeds its preset value, v(b out ) decreases; this causes a higher voltage across r c which, in turn, implies a larger volt- age across r e and a larger reset current i r (v be of q 1 is supposed constant). a larger i r causes the pwm waveform across d 2 to get narrower. this pulls the output voltage back to the desired level and achieves regulation. it is possible to use this section to drive a pass transistor to obtain 3.3v with a linear regulator; in the "application idea" section an example is showed to implement this solution. figure 16. magamp control feedback section C auxiliary section, error amplifier c. this section (fig. 17) provides the feedback signal for the auxiliary converter following the same oper- ating principles as the main section. the auxiliary output voltage (vaux) is often defined as "standby voltage" because the converter remains alive during standby condition (the main converter is stopped) to supply the chip and all the ancillary circuits. typical values for its output voltage are 5v or 3.3v. the inverting input (cinv, pin#7) is connected to the output voltage through an external resistor divider whereas the non-inverting one is connected to a 1.25v trimmable internal voltage reference (see "on board trimming and mode operating" paragraph). the compensation network zc(aux) is placed between e/a inverting input and output pins. when dmon recognizes an undervoltage condition on the auxiliary output, an internal n-channel mos (in open drain configuration) grounds e/a output pin; the high current flowing through the optocoupler is then transferred to the primary side causing a duty cycle as short as possible; this prevents a high energy transfer from primary to secondary under short circuit conditions, thus reducing the thermal stress on the power components. figure 17. auxiliary feedback section +3.3v zc bout binv +1.25v r l r h _ + l6611 ma g amp r c r s r e d 1 i r d 2 v d2 q 1 l c +3.3v zc bout binv +1.25v r l r h _ + l6611 ma g amp r c r s r e d 1 i r d 2 v d2 q 1 l c v aux to aux control zc(aux) cout cinv r b +1.25v r h r l _ + l6611 ocp bounce gnd dmon v aux to aux control zc(aux) cout cinv r b +1.25v r h r l _ + l6611 ocp bounce gnd dmon
l6611 20/28 3 normal operation timing diagram (fig. 18) the time intervals t1-t5 are listed below C t1: uv/oc blanking of mfault. while main outputs are ramping up, the uv comparators are blanked for this interval to prevent a false turn-off. no such blanking is applied to ov faults. C t2: pw-ok delay. this period starts when all monitored outputs and ac sense are above their respec- tive uv levels and finishes at pw-ok going high. C t3: ps-on debounce period. the voltage on ps-on must be continuously present in a high or low state for a minimum period for that state to be recognized. C t4: tdelay. the time from ps-on being recognized as going high to mfault going high. this is to provide a power down warning. when ps-on requests power off, pw-ok goes low immediately. C t5: uv blanking of dfault. during initial power up a period of uv blanking is applied to dfault as soon as vdd to the chip is in the correct range. no such blanking is applied to ov faults. figure 18. normal operation timing diagram (on/off with ps-on or the ac power switch). ac vdd ps-on mfault main ops pok uvbmfault acsns off on on off t3 t1 t2 t4 t3 t2 t1 vdd-ok uvbdfault acsns_high acsns_low vdd(on) vdd(on) t5
21/28 l6611 4 undervoltage, overvoltage, detection and relevant timings the ic provides on-board undervoltage and overvoltage protection for 3v3, 5v, 12v main input pins and dmon auxiliary input pin. overcurrent protection is available for 12v and 5v or 3.3v, digitally selectable. the internal fault logic is illustrated in figure 19. figure 19. simplified fault logic C main inputs overvoltage: whenever one of main outputs (3.3v, +5v, 12v) is detected as going over- voltage, mfault is latched high (which stops the main pwm) and pw-ok goes low. cycling the ps- on switch or reducing vdd below its undervoltage threshold releases the latch. a delay of 6s is imple- mented before mfault latching. the ov protection for the 12v and 5v outputs can be disabled (see "on board trimming and mode op- erating" section). C main inputs undervoltage: when an undervoltage on main outputs is detected, mfault is latched high (the main pwm stops) and pw-ok goes low. the latches are released, by default, cycling the ps- on switch or reducing vdd below its undervoltage threshold (latching mode); optionally, an attempt is made to restart the supply after of 1 second (bounce mode). the choice depends on the selected mode (see "on board trimming and mode operating" section). debounce logic is implemented for 3.3v and 5v so that an undervoltage condition on these signals has to last 450s to be recognized as valid while 6s debounce logic is implemented for 12v and -12v input signal. when all main undervoltages are over and acsns is ok (see the relevant section), pw_ok goes high after a delay of 250ms. C dmon input overvoltage: whenever the dmon input pin is detected as going overvoltage, both mfault and dfault are latched high. the latch is released by reducing vdd below its undervoltage threshold. debounce logic is implemented so that mfault and dfault signals are latched only if the overvoltage condition lasts more than 6s. to protect the load against overvoltage, typical solutions make use of a power crowbar (scr) driven by delay 1s in clock out reset debounce 75ms clock in reset out ps-on restart mode vdd vdd_ov vdd_uvl on clock reset uvb 64ms in out clock reset uvb 64ms in out dmon_uv dmon_ov acsense vref main_ov reset clock in out debounce 6 m s reset clock in out reset clock in out la tch r sq clock in reset out delay 250ms delay 2.5ms reset out clock in vdd pw-ok cout la tch r sq la tch r sq dfault vdd mfault la tch r sq vdd vdd vdd d_uvb reset reset clock in out reset reset reset reset reset reset reset reset reset reset reset clock in out +/-12v_main_uv +3v3 +5v_main_uv debounce 6 m s debounce 500 m s debounce 500 m s debounce 6 m s + delay 1s in clock out reset debounce 75ms clock in reset out ps-on restart mode vdd vdd_ov vdd_uvl on clock reset uvb 64ms in out clock reset uvb 64ms in out dmon_uv dmon_ov acsense vref main_ov reset clock in out debounce 6 m s reset clock in out reset clock in out la tch r sq clock in reset out delay 250ms delay 2.5ms reset out clock in vdd pw-ok cout la tch r sq la tch r sq dfault vdd mfault la tch r sq vdd vdd vdd d_uvb reset reset clock in out reset reset reset reset reset reset reset reset reset reset reset clock in out +/-12v_main_uv +3v3 +5v_main_uv debounce 6 m s debounce 500 m s debounce 500 m s debounce 6 m s +
l6611 22/28 dfault; in the "application ideas" section, another simple circuit is showed to guarantee the same pro- tection without the scr. C dmon input undervoltage: when an undervoltage on dmon is detected, mfault is put high, cout is pulled low (an internal ocp_bounce signal is generated, see fig. 19) and pw_ok falls down. this function is enabled 64ms after the uvlo signal falls down. debounce logic is implemented so that mfault and ocp_bounce signals are generated only if the undervoltage condition lasts more than 500s. the dmon uv and ov protections can be set to work with thresholds set for 5v or 3.3v output voltage: the choice depends on the ic programming. figure 20. fault timing diagram 5 ac sense (mains undervoltage warning) the device monitors the primary bulk voltage and warns the system when the power is about to be lost pulling down the pw_ok output. the acsns pin is typically connected to one of the windings of the main transformer (see fig. 21). through a single-diode rectification filter, a voltage equal to v b = v bulk /n (where v bulk is the voltage across the bulk ca- pacitor on primary side and n is the transformer turn ratio) is present at point b. a resistor (r f ) could be useful to clamp voltage spikes present. the fault signal is generated by means of ac_good, the output of an internal comparator; this comparator is internally referred to a trimmable 2.5v reference and indicates an ac fault if the voltage applied at its externally available (non-inverting) input is below the internal reference, as shown in fig. 21. this comparator is provided with current hysteresis instead of a more usual voltage hysteresis: an internal 50a current generator is on if the voltage is below 2.5v and is turned off when the voltage applied at the non-invert- ing input exceeds 2.5v. this approach provides an additional degree of freedom: it is possible to set the on threshold and the off dmon (*) dmon (*) mfault mfault pok pok dfault current cout output mfault pok main outputs overvoltage output mfault pok main outputs undervoltage auxiliary outputs overvoltage auxiliary outputs undervoltage (*) dmon is connected to the auxiliary output rail
23/28 l6611 threshold separately by properly choosing the resistors of the external divider. the following relationships can be established for the on (vb (on) ) and off (vb (off) ) thresholds of the input voltage: which, solved for r1 and r2, yields: both the acsns threshold and the hysteresis current can be trimmed (see "on board trimming and mode oper- ating" section). figure 21. acsns circuit and timing diagram 6 application example in applications like desktop pc's, server or web server, the system usually consists of two converters (main and auxiliary) that can be supplied directly from either the ac mains or a pfc stage. the control and supervision at the secondary side is usually entrusted to a housekeeping circuit. the auxiliary section supplies a stand-by voltage (5v typ.) through a flyback converter. the main section, in forward configuration, presents 4 standard outputs (3.3v, +5v, 12v). at the secondary side, the housekeeping circuitry governed by the l6611 checks the outputs and sends control signals to the primary side through three optocouplers. it also generates power good information to the system while managing all timings during power-up and power-down sequences. in fig. 22 a detailed circuit for the sec- ondary side is presented; it is possible to note the very low number of external components required. simply connecting the power supply outputs to the l6611 relevant pins ensures the protection against over/un- dervoltage in the main section. a crowbar on the auxiliary output is switched on through dfault in case of overvoltage. the l6611 is supplied by the auxiliary output; the signals sent to the primary side are: C a "digital" on/off signal through an optocoupler that drives the relevant pin of primary main controller to switch the main converter on and off; C two analog signals that provide voltage feedback for both the auxiliary and the main section, driving the primary controller pins responsible for the duty cycle modulation. vb on () 2.5 C r 1 ---------------------------------- 2.5 r 2 ------- - 50 m a + = vb off () r 2 r 1 r 2 + -------------------- 2.5 = r 1 vb on () vb off () C 50 m a ------------------------------------------------ - = r 2 r 1 2.5 vb off () 2.5 C ------------------------------------ - = +2.5v gnd i hys=50 m a _ + ac_good r 1 r 2 c 1 r f b l6611 acsns vb ac_good v acsns vb(on) vb(off) d =50 m a*r 1 d d pw_ok on +2.5v gnd i hys=50 m a _ + ac_good r 1 r 2 c 1 r f b l6611 acsns vb ac_good v acsns vb(on) vb(off) d =50 m a*r 1 d d pw_ok on
l6611 24/28 figure 22. detailed secondary side +5vaux +5v +12v com -12v +3.3v -12 3v3 dmon 12v 5v bout binv m-fault ainv cout ps-on cinv vref aout vdd acsns dfault pw-ok gnd primary side control & power management l6611 prog
25/28 l6611 7 application ideas in fig. 23 a circuit is suggested to obtain the regulated +3.3v output with a linear configuration instead of the magamp circuitry. in this case the output of the e/a modulates the gate-source voltage of a power mos in series with the power stage. in fig. 24 a simple and cheap latch circuit is showed to manage an ov fault on the auxiliary output in the same way of an oc (uv) fault, without having recourse to a (expensive) power crowbar. by tuning the value of r set it is possible to set the voltage value that triggers the latch circuit; c del defines the turn-on delay. a diode con- nected between the collector of q1 and cout pulls down the output of the auxiliary e/a: this has the same effect of the ocp_bounce internal signal that guarantees the reduction of duty cycle. figure 23. controlling a linear regulator with the error amplifier b figure 24. auxiliary ovp without crowbar +3.3v bout binv +1.25v r l r h _ + l6611 +5v r b l c 1 c 2 +12v z c +3.3v bout binv +1.25v r l r h _ + l6611 +5v r b l c 1 c 2 +12v z c l6611 v aux dmon 100 5k6 5k6 q2 bc558 q1 bc548 r set c del cout d1 bat42 l6611 v aux dmon 100 5k6 5k6 q2 bc558 q1 bc548 r set c del cout d1 bat42
l6611 26/28 dip20 dim. mm inch min. typ. max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 d 25.4 1.000 e 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 f 7.1 0.280 i 3.93 0.155 l 3.3 0.130 z 1.34 0.053 outline and mechanical data
27/28 l6611 11 0 11 20 a e b d e l k h a1 c so20mec h x 45? so20 dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.3 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13 0.496 0.512 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k 0? (min.)8? (max.) outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 28/28 l6611

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